Non-volatile memory elements are desirable elements of integrated circuits due to their ability to maintain data absent a supply of power. Various resistance variable materials have been investigated for use in non-volatile memory elements, including chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state and the resistance states can be used to distinguish the logic values of the memory element. Specifically, an amorphous state exhibits a relatively high resistance, while a crystalline state exhibits a relatively low resistance.
Phase-change memory elements are disclosed in pending U.S. patent application Ser. No. 11/396,616, entitled PHASE CHANGE MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MAKING AND USING THE SAME, filed on Apr. 4, 2006 (“the '616 application”), which is incorporated herein in its entirety by reference. One such phase-change memory element 110, illustrated in FIGS. 1A and 1B, has a layer of phase-change material 116 between first and second electrodes 112, 118, which are supported by a dielectric material 114 which has an opening containing the first electrode 112. The phase-change material 116 is set to a particular resistance state according to the amount of current applied by the first and second electrodes 112, 118. To obtain an amorphous state (FIG. 1B), a relatively high write current pulse (a reset pulse) is applied through the conventional phase-change memory element 110 to melt at least a portion 126 of the phase-change material 116 covering the first electrode 112 for a first period of time. The current is removed and the phase-change material 116 cools rapidly to a temperature below the crystallization temperature, which results in the portion 126 of the phase-change material 116 covering the first electrode 112 having the amorphous state. To obtain a crystalline state (FIG. 1A), a lower write current pulse (a set pulse) is applied to the phase-change memory element 110 for a second period of time, which is typically longer in duration than the crystallization time of amorphous phase-change material, to heat the amorphous portion 126 of the phase-change material 116 to a temperature below its melting point, but above its crystallization temperature. This causes the amorphous portion 126 of the phase-change material 116 to re-crystallize to the crystalline state that is maintained once the current is removed and the phase-change memory element 110 is cooled. The phase-change memory element 110 is read by applying a read voltage, which does not change the state of the phase-change material 116.
One potential drawback of the above described phase-change memory element 110 is the large programming current needed to achieve the phase change. This need for the large current is a limitation when attempting to reduce the size of the memory element. Another problem associated with the above described phase-change memory element 110 is heat loss. Since the phase-change material 116 is in direct contact with a large area of the first electrode 112, there may be a significant amount of heat loss resulting in a large reset current requirement. Additionally, since the programmable volume (i.e., portion 126) of the phase-change material 116 is not confined and has the freedom to extend sideways during phase change, switching stability may be reduced.
Accordingly, one technique used to reduce the high current requirement, reduce heat loss, and improve switching stability has been to confine and reduce the programmable volume and reduce the electrode area in contact with the programmable volume. FIG. 2A, also described in the '616 application, illustrates one example of a phase-change memory element 210 designed to address the potential drawbacks of the phase-change memory element 110 illustrated in FIGS. 1A-1B. To fabricate the phase-change memory element 210, as shown in FIG. 2B, a cylindrical via 222 is etched into a second insulating layer 224 to expose a first electrode 212. A layer of phase-change material 216 (FIG. 2C) is deposited along the sidewall 230 of the via 222 to serve as the programmable volume of the phase-change memory element 210. In FIG. 2C, a third insulating layer 228 is deposited over the phase-change material 216 and within the via 222. A subsequent chemical-mechanical planarization (CMP) step removes the phase-change material 216 and the insulating material 228, stopping at the second insulating layer 224. The CMP process exposes a ring 232 of phase-change material 216 which can be covered by and in contact with the second electrode 218 as shown in FIG. 2A.
Referring to FIG. 3, it is known that due to arrival angle distribution and poor step coverage, a conventional physical vapor deposition (PVD) process can not always accurately control the thickness of the phase-change material 316 deposited along the sidewall 330 of a via 322. In addition, a maximum thickness of phase-change material 316 deposited along the sidewall 330 of the via 322 that can be achieved with the conventional PVD process is limited. Once the amount of phase-change material 316 deposited on the sidewall 330 saturates, as shown in FIG. 3, the thickness of the phase-change material on the sidewall 330 does not grow with additional deposition of the phase-change material. Meanwhile, the thickness of the phase-change material on the field region 331 surrounding the via 322 continues to grow forming a thick layer. This thick layer of phase-change material deposited on the field region 331 surrounding the via 322 poses a problem for the subsequent CMP process, as it introduces large film stress and phase-change material adhesion issues during CMP.
It is desirable to obtain a deposition process that can control the thickness of a material deposited on the sidewall of a via without introducing problems in the overall process flow.